The need for gate input protection and ESD protection circuitry has long been recognized. For CMOS circuits and silicon MOSFET power devices and systems, arrangements of Zener diodes may be used for overvoltage and ESD protection of the gates of MOSFET devices (see for example “Low-Side Self Protected MOSFET”, ON Semiconductor Application note, February 2011).
US2014/0092508 (Ko) discloses a clamping circuit which detect a change in level of a gate voltage due to ESD, and clamps the gate voltage of the high voltage transistor.
US2013/0127500 (Kobayishi) discloses a circuit such that when an electric discharge is generated between the drain terminal and the gate control terminal of a power transistor the gate of the power semiconductor device is charged to turn on and absorb the surge energy, i.e. suppress the surge voltage applied to the drain terminal and prevent breakdown of the power semiconductor device.
For power switching applications, large area, lateral GaN transistors of many performance benefits, e.g. low on-resistance, high current capability, higher Figure of Merit (FOM), relative to Si power MOSFETS and IGBTs. Thus lateral GaN power transistors systems are being developed rapidly and gaining traction for applications such as switching circuitry for electric vehicles. However, gate input protection and ESD protection of lateral GaN power transistors is a particular challenge relative to MOSFET power devices.
On the other hand, the gate of a lateral GaN power transistor has a relatively low ESD rating, which means that the gate structure is relatively “fragile”, i.e. more sensitive to overvoltage spikes compared to the gate structure of MOSFET power devices. Despite other advantages of lateral GaN power devices, for some applications, this issue may be potential disadvantage and creates a significant handling problem.
As disclosed in US patent publication no. 2014/0015591 (Chen), gate voltage limiting and transient voltage suppression for group III-nitride semiconductor devices such as GaN HEMTs can be achieved with discrete silicon Zener diodes. However, integrated Zener diodes with a suitable Zener breakdown voltage cannot be fabricated using a GaN hetero-structure. Thus Chen discloses providing gate protection to a group III—semiconductor device by embedding a gate-voltage-controlling second transistor, in series with the gate electrode of a first transistor. The gate-voltage-controlling second transistor may be gate-source connected depletion mode GaN transistor. That, is first gate electrode of the first semiconductor device is in series with a second source electrode of the second semiconductor device, and a second gate electrode of the second semiconductor device is connected to the second source electrode and the first gate electrode.
Based on ESD testing of large area, E-mode lateral GaN power transistors, the present Applicant/Inventors have observed that positive ESD voltage spikes on the gate are better tolerated, since the gate is more robust in that direction, while ESD damage tends to be caused by negative voltage spikes on the gate. Prior art solutions, such as the above references, focus on protection against positive spikes rather than negative spikes.
Thus, there is a need to improved ESD protection for the gate input of GaN power transistors, particularly for protection against negative voltage spikes.